REV. 0

AD9410

–6–

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Function

1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24,

AGND

Analog Ground.

27, 28, 29, 30, 71, 72, 73, 74, 77, 78

3, 7, 14, 15

5 V Supply. (Regulate to within

±5%.)

4

Internal Reference Output.

5

Internal Reference Input.

6

DNC

Do Not Connect.

10

Analog Input—True.

11

AIN

Analog Input—Complement.

18

ENCODE

Clock Input—True.

19

ENCODE

Clock Input—Complement.

22

DS

Data Sync (Input)—True. Tie LOW if not used.

23

DS

Data Sync (Input)—Complement. Float and decouple with 0.1

µF

capacitor if not used.

25, 26, 31, 32, 69, 70, 75, 76

3.3 V Analog Supply. (Regulate to within

±5%.)

33, 40, 49, 52, 59, 68

DGND

Digital Ground.

34, 41, 48, 53, 60, 67

3.3 V Digital Output Supply. (2.5 V to 3.6 V)

35–39

42–46

47

Data Overrange for Channel B.

50

DCO

Clock Output—Complement.

51

DCO

Clock Output—True.

54–58

61–65

66

Data Overrange for Channel A.

79

DFS

Data Format Select. HIGH = Two’s Complement, LOW = Binary.

80

I/P

Interleaved or Parallel Output Mode. Low = Parallel Mode, High =

Interleaved Mode. If tying high, use a current limiting series resistor

(2.5 k

Ω) to the 5 V supply.