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ICS950812 データシート(PDF) 2 Page - Integrated Circuit Systems

部品番号 ICS950812
部品情報  Frequency Generator with 200MHz Differential CPU Clocks
PDF  29 Pages
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メーカー  ICST [Integrated Circuit Systems]
ホームページ  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS950812 データシート(HTML) 2 Page - Integrated Circuit Systems

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ICS950812
0542G—08/21/03
Pin Configuration
PIN # PIN NAME
PIN TYPE
DESCRIPTION
1
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
2
X1
IN
Crystal input, Nominally 14.318MHz.
3
X2
OUT
Crystal output, Nominally 14.318MHz
4
GND
PWR
Ground pin.
5
PCICLK_F0
OUT
Free running PCI clock not affected by PCI_STOP# .
6
PCICLK_F1
OUT
Free running PCI clock not affected by PCI_STOP# .
7
PCICLK_F2
OUT
Free running PCI clock not affected by PCI_STOP# .
8
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
9
GND
PWR
Ground pin.
10
PCICLK0
OUT
PCI clock output.
11
**E_PCICLK1/PCICLK1
I/O
Early/Normal PCI clock output latched at power up.
12
PCICLK2
OUT
PCI clock output.
13
**E_PCICLK3/PCICLK3
I/O
Early/Normal PCI clock output latched at power up.
14
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
15
GND
PWR
Ground pin.
16
PCICLK4
OUT
PCI clock output.
17
PCICLK5
OUT
PCI clock output.
18
PCICLK6
OUT
PCI clock output.
19
VDD3V66
PWR
Power pin for the 3V66 clocks.
20
GND
PWR
Ground pin.
21
66MHZ_OUT0/3V66_2
OUT
3.3V 66.66MHz clock output selected via buffered or internal VCO.
22
66MHZ_OUT1/3V66_3
OUT
3.3V 66.66MHz clock output selected via buffered or internal VCO.
23
66MHZ_OUT2/3V66_4
OUT
3.3V 66.66MHz clock output selected via buffered or internal VCO.
24
66MHZ_IN/3V66_5
I/O
3.3V 66.66MHz clock from internal VCO, 66MHZ input to 66MHz output and
PCI.
25
*PD#
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal
are stopped. The latency of the power down will not be greater than 1.8ms.
26
VDDA
PWR
3.3V power for the PLL core.
27
GND
PWR
Ground pin.
28
Vtt_PWRGD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.



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