ECT25S40 datasheet(26/46 Pages) E-CMOS

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E-CMOS Corp. (www.ecmos.com.tw)

Page 26 of 46

4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

JEDEC ID (9FH)

The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by

Two bytes of device identification. The device identification indicates the memory type in the

first byte, and the memory capacity of the device in the second byte. JEDEC ID instruction

while an Erase or Program cycle is in progress, is not decoded, and has no effect on the

cycle that is in progress.

The JEDEC ID instruction should not be issued while the device is in Deep Power-Down Mode.

See Figure 21, he device is first selected by driving /CS to low. Then, the 8-bit instruction code

For the instruction is shifted in. This is followed by the 24-bit device identification, stored in the

memory, being shifted out on Serial Data Output, each bit being shifted out during the falling

edge of Serial Clock. The JEDEC ID instruction is terminated by driving /CS to high at any

time during data output. When /CS is driven high, the device is put in the Standby

Mode.

Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and

execute instructions.

Figure 21. JEDEC ID Sequence Diagram

ECT25S40 データシート(PDF) 26 Page - E-CMOS Corporation