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AD9652BBCZ-310 データシート(PDF) 8 Page - Analog Devices |
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AD9652BBCZ-310 データシート(HTML) 8 Page - Analog Devices |
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8 / 37 page  Data Sheet AD9652 Rev. B | Page 7 of 36 SWITCHING SPECIFICATIONS Table 4. Parameter Test Conditions/Comments Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS (CLK±) Input Clock Rate Full 80 1240 MHz Conversion Rate1 Full 80 310 MSPS Period—Divide by 1 Mode (tCLK) Full 3.2 ns Pulse Width High (tCH), Minimum Divide by 1 Mode DCS enabled Full 0.8 ns DCS disabled Full 1.3 ns Divide by 2 Mode Through Divide by 8 Mode Full 0.8 ns Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms DATA OUTPUT PARAMETERS LVDS Mode Data Propagation Delay (tPD) Full 290 ps DCO± Propagation Delay (tDCO) Full 290 ps DCO± to Data Skew (tSKEW) Full −80 −280 −480 ps2 Pipeline Delay (Latency) Full 26 Cycles Wake-Up Time From standby Full 100 μs From power-down Full 1 sec Out of Range Recovery Time Full 3 Cycles 1 Conversion rate is the clock rate after the divider. 2 Data transitions prior to DCO± edge transition. TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to the rising edge of CLK+ setup time 0.1 ns tHSYNC SYNC to the rising edge of CLK+ hold time 0.1 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK is in a logic high state 10 ns tLOW Minimum period that SCLK is in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Timing Diagrams) 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Timing Diagrams) 10 ns tSPI_RST Time required after power-up, hard or soft reset until SPI access is available (not shown in Timing Diagrams) 500 μs |
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