AD7989-5BCPZ-R2 datasheet(17/24 Pages) AD

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Data Sheet

AD7989-1/AD7989-5

Rev. B | Page 17 of 24

CS MODE, 3-WIRE

This mode is usually used when a single AD7989-1/AD7989-5

is connected to an SPI-compatible digital host. The connection

diagram is shown in Figure 31, and the corresponding timing is

given in Figure 32.

With SDI/CS tied to VIO, a rising edge on CNV initiates a

conversion, selects the CS mode, and forces SDO to high

impedance.

When the conversion is complete, the AD7989-1/AD7989-5 enter

the acquisition phase and power down. When CNV goes low, the

MSB is output onto SDO. The remaining data bits are clocked by

subsequent SCK falling edges. The data is valid on both SCK edges.

Although the rising edge can capture the data, a digital host using

the SCK falling edge allows a faster reading rate, provided that it

has an acceptable hold time. After the 18th SCK falling edge or

when CNV goes high (whichever occurs first), SDO returns to

high impedance.

Figure 31. CS Mode, 3-Wire Connection Diagram (SDI High)

Figure 32. CS Mode, 3-Wire Serial Interface Timing (SDI High)

AD7989-1/

AD7989-5

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

SDI/CS

SDO

D17

D16

D15

tDIS

SCK

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

CNV

CONVERSION

ACQUISITION

tCONV

tCYC

ACQUISITION

tACQ

tEN

SDI/CS = 1

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