PC87435 datasheet(3/5 Pages) NSC

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Features (Continued)

Host Controlled Function Features

LPC System Interface

— Synchronous cycles, up to 33 MHz bus clock

— Serial IRQ

— I/O and Memory read and write cycles

— LPC and FWH read cycles

Base Address (BADDR) strap to determine the base

address

the

conﬁguration

Index-Data

pairPC01 and ACPI Compliant

— PnP Conﬁguration Register structure

— Flexible resource allocation for all logical devices

❏

Relocatable base address

❏

15 IRQ routing options

— Generates SCI (PWUREQ) for ACPI systems

Shared Memory and Protection

— Bridges LPC access to internal and expansion

memory

— CR16B controlled, LPC access protection

— FWH transaction support

Real-Time Clock (RTC)

System Wake-Up Control (SWC)

— Wake-up on detection on:

— Software controlled off events

— Optional routing of power-up request to IRQ, SMI

and SCI (PWUREQ) lines

Clocking, Supply and Package Information

Strap Input Controlled Operating Modes

— TRI-STATE of all the pins

— Development (ISE/ADB)

— On-board development

— Programing Environment

Clocks

— Single 32.768 KHz crystal oscillator

— On-chip high frequency clock generator

❏

CPU clock 4-20 MHz

❏

Software-controlled frequency generation

❏

Based on the 32.768 KHz input

— 32.768 KHz clock output

— CPU clock output

Power Management Control (PMC)

— Separate

3.3V

supply

for

the

CPU

and

its

peripherals (VCC), Analog (AVCC) and for the other

functions (VDD)

— All pins are 5V tolerant and back-drive protected

(except the LPC bus pins)

— Backup battery input for RTC, and wake-up conﬁgu-

ration

— Reduced power consumption capability

— Automatic wake-up on system events

Package options

— 176-pin LQFP package for Expansion Memory use

and development

— 128-pin LQFP package for a minimal BMC

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