AD9268 datasheet(40/45 Pages) AD

40 / 45 page

AD9268

Rev. A | Page 39 of 44

Address

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default

Notes/

Comments

0x0E

BIST enable

(global)

Open

Reset BIST

sequence

Open

BIST

enable

0x04

0x0F

ADC input

(global)

Open

Common-

mode

servo

enable

0x00

0x10

Offset adjust

(local)

Offset adjust in LSBs from +127 to −128

(twos complement format)

0x00

0x14

Output mode

Drive

strength

0 = ANSI

LVDS;

1 =

reduced

swing

LVDS

(global)

Output

type

0 = CMOS

1 = LVDS

(global)

CMOS

output

interleave

enable

(global)

Output

enable

bar

(local)

Open

(must be

written

low)

Output

invert

(local)

Output format

00 = offset binary

01 = twos

complement

01 = gray code

11 = offset binary

(local)

0x00

Configures the

outputs and

the format of

the data

0x16

Clock phase

control

(global)

Invert

DCO clock

Open

Input clock divider phase adjust

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

0x00

Allows

selection of

clock delays

into the input

clock divider

0x17

DCO output

delay (global)

Open

DCO clock delay

(delay = 2500 ps × register value/31)

00000 = 0 ps

00001 = 81 ps

00010 = 161 ps

…

11110 = 2419 ps

11111 = 2500 ps

0x00

0x18

VREF select

(global)

Reference voltage

selection

00 = 1.25 V p-p

01 = 1.5 V p-p

10 = 1.75 V p-p

11 = 2.0 V p-p

(default)

Open

0xC0

0x24

BIST signature

LSB (local)

BIST signature[7:0]

0x00

Read only

0x25

BIST signature

MSB (local)

BIST signature[15:8]

0x00

Read only

0x30

Dither enable

(local)

Open

Dither

enable

Open

0x00

Digital Feature Control

0x100

Sync control

(global)

Open

Clock

divider

next sync

only

Clock

divider

sync

enable

Master

sync

enable

0x00

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