MP8775AS datasheet(5/8 Pages) EXAR

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MP8775

Rev. 3.01

N + 1

N--1

Output

Codes

Analog

Input

Code Width (N) = V(N+1) -- V(N)

LSB = [ VRT -- VRB ] / 256

DNL(N) = [ V(N+1) -- V(N) ] -- LSB

Figure 2. DNL Measurement

LSB

DNL

Output

Codes

Analog Input (Volt)

Figure 3. INL Error Calculation

Best Fit Line

EFS

EZS

LSB

Ideal Transfer Line

Real Transfer Line

INL

V(N+1)

V(N)

Figure 4. Equivalent Input Circuit

VRT + VRB

CLK

5pF

1.5pF

CLK

5pF

1.5pF

VIN [N--2]

AVDD

VIN

6 pF

Figure 5. Typical Circuit Connections

Analog

Input

0.1

+5 V

Clock

VIN

VDD

VRTS

VRT

VRB

VRBS

GND

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CLK

MP8775

Digital

Outputs

AGND

APPLICATION NOTES

Signals should not exceed AVDD +0.5V or go below AGND

--0.5V or DVDD +0.5 V or DGND --0.5 V. All pins have internal

protection diodes that will protect them from short transients

(<100ms) outside the supply range.

AGND and DGND pins are connected internally through the

P-- substrate. DC voltage differences between these pins will

cause undesirable internal substrate currents.

The power supply (AVDD) and reference voltage (VRT & VRB)

pins should be decoupled with 0.1mF and 10mF capacitors to

AGND, placed as close to the chip as possible.

The digital outputs should not drive long wires or buses. The

capacitive coupling and reflections will contribute noise to the

conversion.

It is possible for the data valid delay (tDL) to be equal to or

greater than the high pulse width of the sampling clock (tPWH),

See

Figure 1. This can cause timing related errors. For sample

rates above 14 MSPS use only the rising edge of the sample

clock (CLK) to latch data from the MP8775 to other parts of the

system.

The reference can be biased internally by shorting VRT to

VRTS and VRB to VRBS. This will generate 0.6 V at VRB and 2.6 V

at VRT (see Figure 5.).

If the internal reference pins VRTS and/or VRBS are not used

they should be left unconnected.

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