HD74AC datasheet(49/52 Pages) HITACHI

49 / 52 page

Design Considerations

Since the static I

CC requirements of CMOS devices are so low, output load currents must be prevented from

masking the current load of the device during an I

CC test. Even a standard 500 Ω load resistor will sink 10

mA at 5 V, which is more than twice the I

CC level being tested. Thus, most manufacturers will specify that

all outputs must be unloaded during I

CC tests.

Another area of concern is identified when considering the inputs of the device. When the input is in the

transition region, I

CC can be several orders of magnitude greater than the specification. When the input

voltage is in the transition region, both the n-channel and the p-channel transistors in the input totem-pole

structure will be slightly on, and a conduction is created from V

CC to ground. This conduction path leads to

the increased I

CC current seen in the ICC vs. VIN curve (figure 22). When the input is at either rail, the input

structure no longer conducts. Most I

CC testing is done with all of the inputs tied to either VCC or ground. If

the inputs are allowed to float, they will typically float to the middle of the transition region, and the input

structure will conduct an order of magnitude more current than the actual I

CC of the device under test which

is being measured by the tester.

When testing the I

CC of a CMOS HD74AC245/HD74ACT245, problems can arise depending upon how the

test is conducted. Note the structure of the HD74AC245/HD74ACT245’s I/O pins illustrated figure 23.

10.00

0.00

5.00

VIN(V)

Figure 22 I

CC versus IIN

Drive Enable

I/O PAD

Figure 23 HD74AC245/HD74ACT245 I/O Structure

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