M41ST87Y datasheet(14/42 Pages) STMICROELECTRONICS

部品番号	M41ST87Y

部品情報	5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection

PDF	42 Pages

Scroll/Zoom	100%

メーカー	STMICROELECTRONICS [STMicroelectronics]

ホームページ	http://www.st.com

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14 / 42 page

M41ST87Y, M41ST87W

14/42

WRITE Mode

In this mode the master transmitter transmits to

the M41ST87Y/W slave receiver. Bus protocol is

shown in Figure 12., page 14. Following the

START condition and slave address, a logic '0' (R/

W=0) is placed on the bus and indicates to the ad-

dressed device that word address An will follow

and is to be written to the on-chip address pointer.

The data word to be written to the memory is

strobed in next and the internal address pointer is

incremented to the next memory location within

the RAM on the reception of an acknowledge

clock. The M41ST87Y/W slave receiver will send

an acknowledge clock to the master transmitter af-

ter it has received the slave address (see Figure

9., page 12) and again after it has received the

word address and each data byte.

Figure 12. WRITE Mode Sequence

Figure 13. WRITE Cycle Timing: RTC & External SRAM Control Signals

AI00591

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

AI03663

ECON

tEXPD

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