AD7674ASTZL datasheet(21/29 Pages) AD

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AD7674

Data Sheet

Rev. B | Page 20 of 28

FREQUECY (kHz)

100

1000

10000

03083-0-032

Figure 33. PSRR vs. Frequency

POWER DISSIPATION VERSUS THROUGHPUT

In Impulse mode, the AD7674 automatically reduces its power

consumption at the end of each conversion phase. During the

acquisition phase, the operating currents are very low, which

allows for a significant power savings when the conversion rate

is reduced, as shown in Figure 34. This feature makes the AD7674

ideal for very low power battery applications. It should be noted

that the digital interface remains active even during the acquisition

phase. To reduce the operating digital supply currents even

further, the digital inputs need to be driven close to the power

rails (DVDD and DGND), and OVDD should not exceed

DVDD by more than 0.3 V.

SAMPLING RATE (SPS)

1000000

100000

10000

1000

100

0.1

100k

10k

100

WARP/NORMAL

PDBUF HIGH

03083-0-033

IMPULSE

Figure 34. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

Figure 35 shows the detailed timing diagrams of the conversion

process. The AD7674 is controlled by the CNVST signal, which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by PD, until the conversion is complete. The

CNVST signal operates independently of CS and RD signals.

CNVST

MODE

ACQUIRE

CONVERT

ACQUIRE

CONVERT

BUSY

03083-0-034

Figure 35. Basic Conversion Timing

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges and levels with minimum

overshoot and undershoot or ringing.

For applications where SNR is critical, the CNVST signal should

have very low jitter. This may be achieved by using a dedicated

oscillator for CNVST generation, or to clock it with a high

frequency low jitter clock, as shown in Figure 28.

In Impulse mode, conversions can be initiated automatically. If

CNVST is held low when BUSY goes low, the AD7674 controls

the acquisition phase and automatically initiates a new conversion.

By keeping CNVST low, the AD7674 keeps the conversion process

running by itself. Note that the analog input has to be settled

when BUSY goes low. Also, at power-up, CNVST should be

brought low once to initiate the conversion process. In this

mode, the AD7674 can sometimes run slightly faster than the

guaranteed limits of 570 kSPS in Impulse mode. This feature

does not exist in Warp or Normal modes.

DIGITAL INTERFACE

The AD7674 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7674 digital interface also accommodates both 3 V and 5 V

logic by simply connecting the OVDD supply pin of the AD7674

to the host system interface digital supply. Finally, by using the

OB/2C input pin in any mode but 18-bit interface mode, both

twos complement and straight binary coding can be used.

The two signals, CS and RD, control the interface. When at least

one of these signals is high, the interface outputs are in high

impedance. Usually, CS allows the selection of each AD7674 in

multicircuit applications, and is held low in a single AD7674

design. RD is generally used to enable the conversion result on

the data bus.

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