ACE24CP02C

I

2

C-Compatible Serial EEPROM

VER 1.1

7

Soft Reset

After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following

these steps: (a) Create a start condition, (b) Clock nine cycles, and (c) create another start bit followed by

stop bit condition, as shown below. The device is ready for the next communication after the above steps

have been completed.

Device Addressing

The ACE24CP02C requires an 8-bit device address word following a start condition to enable the chip for

a read or write operation (see Table Below). The device address word consists of a mandatory one-zero

sequence for the first four most-significant bits, as shown.

Device Address

Access area

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Normal Area

1

0

1

0

E2

E1

E0

R/W

Word Address

Data

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Normal Area

A7

A6

A5

A4

A3

A2

A1

A0

The E2, E1, and E0 device address bits allow as many as eight devices on the same bus. These bits must

compare to their corresponding hardwired input pins.

The E2, E1, and E0 pins use an internal proprietary circuit that biases them to a logic low condition if the

pins are floating.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the

Chip will output a zero. If a compare is not made, the device will return to a standby state.

Data Security

ACE24CP02C has a hardware data protection scheme that allows the user to write protect the whole

Figure6：Soft Reset