ACE24AC32D

Two-wire Serial EEPROM

VER 1.2

6

(B)

Page Write

The 32K EEPROM are capable of 32-byte page write.

A page write is initiated the same way as a byte write, but the microcontroller does not send a stop

condition after the first data word is clocked in. The microcontroller can transmit up to 31 more data

words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond

with a “0” after each data word is received. The microcontroller must terminate the page write

sequence with a stop condition (see Figure 4).

The lower five bits of the data word address are internally incremented following the receipt of each

data word. The higher data word address bits are not incremented, retaining the memory page row

location. If more than 64

data words are transmitted to the EEPROM, the data word address will “roll

over” and the previous data will be overwritten.

(C)

Acknowledge Polling

Acknowledge polling may be used to poll the programming status during a self-timed internal

programming. By issuing a valid read or write address command, the EEPROM will not acknowledge

at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the

programming completes and the chip has returned to the standby mode, the device will return a valid

acknowledge signal at the 9

Read Operations

The read command is similar to the write command except the 8

th

read/write bit in address word is set to

“1”. The three read operation modes are described as follows:

(A)

Current Address Read

The EEPROM internal address word counter maintains the last read or write address plus one if the

power supply to the device has not been cut off. To initiate a current address read operation, the

micro- controller issues a start bit and a valid device address word with the read/write bit (8

th

) set to

“1”. The EEPROM will response with an acknowledge signal on the 9th serial clock cycle. An 8-bit

data word will then be serially clocked out. The internal address word counter will then automatically

increase by one.

For current address read the micro-controller will not issue an acknowledge signal

on the 18

th

clock cycle. The micro-controller issues a valid stop bit after the 18

th

clock cycle to

terminate the read operation.

The device then returns to standby mode (see Figure 5).

(B)

Sequential Read

The sequential read is very similar to current address read. The micro-controller issues a start bit

and a valid device address word with read/write bit (8

th) set to “1”. The EEPROM will response with

an acknowledge signal on the 9

th

serial clock cycle.

An 8-bit data word will then be serially clocked

out. Meanwhile the internally address word counter will then automatically increase by one.

Unlike current address read, the micro-controller sends an acknowledge signal on the 18

th

clock

cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the