1. Overview:

️· The document is an excerpt from the GD25VQ80C Flash memory datasheet.
️· It covers functionality related to status register bits, block protection, hardware protection, and quad mode operation.

2. Status Register Bits (Table Summary):

Bit	Name	Description
S15	SUS	Erase/Program Suspend status (set by Erase/Program Suspend command; cleared by Erase/Program Resume)
S14	CMP	Chip Mode Protection bit. Works with BP4-BP0 for array protection (default: 0).
S13	HPF	High Performance Flag (HPM). 1=HPM enabled; 0=not enabled (default).
S12-S11	Reserved	Reserved for future use.
S10	LB	Security Register Lock-down bit (OTP). 1=Security Registers read-only. (Default: 0)
S9	QE	Quad Enable bit. 0=WP# and HOLD# enabled; 1=Quad IO2 and IO3 enabled. Should not be set to 3 during standard SPI or Dual SPI operation.
S8	SRP1	Status Register Protection bit 1. Part of hardware protection scheme. (See SRP Table below)
S7	SRP0	Status Register Protection bit 0. Part of hardware protection scheme. (See SRP Table below)
S6-S5	Reserved	Reserved for future use.
S4	BP1	Block Protection bit 1. Software protection of memory blocks.
S3	BP0	Block Protection bit 0. Software protection of memory blocks.
S2-S1	BP4-BP3	Block Protection bits. Software protection of memory blocks.
S0	WIP	Write In Progress. 1=busy; 0=idle.
S0	WEL	Write Enable Latch. 1=enabled; 0=disabled.

3. Status Register Protection (SRP) Table:

This table explains how the SRP1 and SRP0 bits affect the write protection status.

SRP1	SRP0	#WP (WP# pin)	Status Register	Description
0	0	X	Software Protected	Status Register writable after Write Enable command (WEL=1). (Default)
0	1	0	Hardware Protected	Status Register locked and cannot be written to when WP# is low.
0	1	1	Hardware Unprotected	Status Register unlocked and writable after Write Enable command (WEL=1)
1	0	X	Power Supply Lock-Down	Status Register protected; requires Power-Down/Power-Up to change.
1	1	X	One Time Program	Status Register permanently protected.

4. Block Protection:

️· The BP4-BP0 bits are non-volatile bits that define protected memory blocks.
️· When set to '1', these blocks are protected from Program, Erase, and certain write commands.
️· They can only be written with a Write Status Register command if hardware protection isn't enabled.

5. Quad Mode Operation:

️· Controlled by the QE (Quad Enable) bit.
️· When QE=0, the WP# (Write Protect) and HOLD# pins are active.
️· When QE=1, Quad IO2 and IO3 are enabled.
️· Important Caution: Do not set QE=1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are connected to power or ground.