GD25VQ80C datasheet(32/55 Pages) GIGADEVICE

部品番号	GD25VQ80C

部品情報	Uniform Sector Dual and Quad Serial Flash

PDF	55 Pages

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メーカー	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

ホームページ	http://www.gigadevice.com/

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32 / 55 page

Uniform Sector

Dual and Quad Serial Flash

GD25VQ80C

Figure 27. High Performance Mode Sequence Diagram

7.25.

Continuous Read Mode Reset (CRMR) (FFH)

The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce

command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the

BBH/EBH/E7H command code.

Because the GD25V

Q80C has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the

GD25VQ80C will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the

Continuous Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence

is show in Figure28.

Figure 28. Continuous Read Mode Reset Sequence Diagram

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

FFH

Mode Bit Reset for Quad/Dual I/O

Don`t Care

Command

A3H

CS#

SCLK

29 30 31

MSB

3 Dummy Bytes

23 22

High Performance Mode

HPM

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