DESCRIPTION
The M36DR432 is a multichip memory device containing a 32 Mbit boot block Flash memory and a 4 Mbit of SRAM. The device is offered in a Stacked LFBGA66 (0.8 mm pitch) package.
The two components are distinguished by use with three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM. The two components are also separately power supplied and grounded.

FEATURES SUMMARY
■ SUPPLY VOLTAGE
    – VDDF = VDDS =1.9V to 2.1V
    – VPPF = 12V for Fast Program (optional)
■ ACCESS TIME: 85,100ns
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
    – Manufacturer Code: 20h
    – Top Device Code, M36DR432C: 00A4h
    – Bottom Device Code, M36DR432D: 00A5h

FLASH MEMORY
■ 32 Mbit (2Mb x16) BOOT BLOCK
    – Parameter Blocks (Top or Bottom Location)
■ PROGRAMMING TIME
    – 10µs typical
    – Double Word Programming Option
■ ASYNCRONOUS PAGE MODE READ
    – Page width: 4 Word
    – Page Mode Access Time: 35ns
■ DUAL BANK OPERATION
    – Read within one Bank while Program or Erase within the other
    – No Delay between Read and Write Operations
■ BLOCK PROTECTION ON ALL BLOCKS
    – WPF for Block Locking
■ COMMON FLASH INTERFACE
    – 64 bit Security Code

SRAM
■ 4 Mbit (256K x 16 bit)
■ LOW VDDS DATA RETENTION: 1V
■ POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS