CS5954AM
ADVANCE
INFORMATION
Document #: 38-08025 Rev. **
Page 13 of 44
4.10
Processor Control Registers
The CS5954AM provides software control registers that can be used to configure the chip mode, clock control, read software
version, and software breakpoint control.
4.10.1
Configuration Register (0xC006: R/W)
The Configuration Register is used to configure the CS5954AM into the appropriate mode, and to select a clock multiplier.[8]
D3
CD
If Clock Disable bit = “1,” this Clock Configuration register can no longer be modified through software writes. It is a “sticky
bit” used to lock the configuration through a write to this bit in the boot prom code.
• On the CS5954AM chip set, this bit will be set to zero.
• There is one mode defined in this document: general-purpose IO (GPIO) mode.
D2, D1
M1,M0:
CS5954AM modes are selected as shown here.
D0
MD
If Mode Disable bit = “1,” this Configuration register can no longer be modified through software writes. It is a “sticky bit”
used to lock the configuration through a Write to this bit in the boot prom code.[9]
D15-D7
Reserved
should be set to all zeros
where
PCLK
is connected to the CS5954AM processor clock.
RCLK
is the resulting clock that connects to other modules (i.e., USB engine).
OE
when OE = 1, the X_PCLK (pin 59) will become an output pin of the PCLK value.
• When the XIN input pin is fed with a 12-MHz signal, the software should set C2 to “1” to enable the PLL.
• X_PCLK is a bidirectional pin allowing an additional clock input for PCLK when selected or an observation pin for
PCLK when OE = “1.”
• The X_PCLK can be used as the input clock like XIN, but only when mode C2=0, C1=1, C0=0.
• Upon reset, the CS5954AM BIOS will set this register equal to 0x0010 (i.e., C2=0, C1=0, C0=1, PCLK=XIN, RCLK=XIN,
OE=0, M1–M0=0=GPIO Mode).
Notes:
8.
D6–4 and C2–0 are Clock Configuration bits. These bits select the clock source. The clock may come from an outside pin (XIN or X_PCLK) or it may come from
the PLL multiplier, as indicated in the table.
9.
By default, this bit will be set to zero by the CS5954AM BIOS.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00
0000000
C2
C1
C0
CD
M1
M0
MD
C2
C1
C0
PCLK
RCLK
OE
00
0
XIN
XIN
0
0
0
1
2/3*XIN
XIN
0
01
0
X_PCLK
XIN
0
0
1
1
2/3*XIN
XIN
1
10
0
4*XIN
4*XIN
0
1
0
1
8/3*XIN
4*XIN
0
11
0
4*XIN
4*XIN
1
1
1
1
8/3*XIN
4*XIN
1
M1
M0
Mode
00
GPIO
01
Reserved
10
Reserved
11
Reserved
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
