CS5954AM
ADVANCE
INFORMATION
Document #: 38-08025 Rev. **
Page 21 of 44
4.14.3
Watchdog Timer Count and Control Register (0xC00C: R/W)
The CS5954AM provides a Watchdog timer to monitor certain activities. The Watchdog timer can also interrupt the CS5954AM
processor. The default value of this register is 0x0000.[21, 22, 23]
D5
WT
Watchdog Time-out occurred.
D4–3TO1–0
Time-out Count:
00
01 milliseconds
01
04 milliseconds
10
16 milliseconds
11
64 milliseconds
D2
EP
Enable Permanent WD timer. If set =”1”
WD timer is always enabled. Cleared only on Reset.
D1
ENB
Enable WD Timer operation when =”1.”
D0
RC
Reset Count. When set =”1.”
4.15
Special GPIO Function for Suspend, Resume and Low-power Modes
The CS5954AM CPU supports suspend, resume, and CPU low-power modes. The CS5954AM BIOS assigns GPIO29 for the
USB DATA+ line pull-up (this pin can simulate USB cable removal or insertion while USB power is still applied to the circuit) and
the GPIO20 for controlling power-off function. The GPIO20 can be used for device low-power mode: it will remove power from
the peripherals in suspend mode. Once USB power is restored, the power to the peripherals may be enabled. The CS5954AM
BIOS will execute the pull-up interrupt upon power-up. To use this feature, the GPIO29 pin must be connected to the DATA+ line
of the USB connector (see Figure 4-5 below). For more information about this function, see [Ref. 1] SL11R_BIOS.
5.0
CS5954AM Interface Modes
The CS5954AM has a general-purpose I/O mode.[24]
5.1
General-purpose I/O Mode (GPIO)
In GPIO mode, the CS5954AM has up to 32 general-purpose I/O signals available. However, there are four pins used by the
2-wire serial interface that cannot be used as GPIO pins. The CS5954AM executes at 48MHz. Other available general-purpose
I/O pins can be programmed for peripheral control and/or status, etc.
The following registers are used for all pins configured as GPIO. The outputs are enabled in the I/0 Control registers. Note that
the output Data can be read back via the Output Data Register even if the outputs are not enabled.
Notes:
21. In order to avoid Watchdog trigger, Reset Count (RC) must be asserted before time-out occurs.
22. The Watchdog Timer overflow causes an internal processor reset. The Processor can read the WT bit after exiting reset to determine if the WT bit is set. If it is
set, a Watchdog time-out occurred.
23. The WT value will be cleared on the next external reset.
24. The 2-wire serial interface IO pins are fixed in all CS5954AM Interface modes.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
000
00
0
0
0
0
WT
TO1
TO0
ENB
EP
RC
USB type B Connector
1
2
3
4
VCC
D-
D+
GND
33
Ω
33
Ω
GPIO29
1.5 K
Ω
Figure 4-5. Special GPIO Pull-up Connection Example
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