BLUENRG-2 datasheet(40/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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address used for the first transfer is the base peripheral/memory address programmed

in the DMA_CPARx or DMA_CMARx register



The storage of the data loaded to the peripheral data register or a location in memory

addressed through an internal current peripheral/memory address register. The start

address used for the first transfer is the base peripheral/memory address programmed

in the DMA_CPARx or DMA_CMARx register



The post-decrementing of the DMA_CNDTRx register, which contains the number of

transactions that have still to be performed.

3.7.2.2

Arbiter

The arbiter manages the channel requests based on their priority and launches the

peripheral/memory access sequences.

The priorities are managed in two stages:



Software: each channel priority can be configured in the DMA_CCRx register. There

are four levels:



Very high priority



High priority



Medium priority



Low priority



Hardware: if two requests have the same software priority level, the channel with the

lowest number will get priority versus the channel with the highest number. For

example, channel 2 gets priority over channel 4.

3.7.2.3

DMA channels

Each channel can handle DMA transfer between a peripheral register located at a fixed

address and a memory address. The amount of data to be transferred (up to 65535) is

programmable. The register, which contains the amount of data items to be transferred, is

decremented after each transaction.

Programmable data sizes

Transfer data sizes of the peripheral and memory are fully programmable through the

PSIZE and MSIZE bits in the DMA_CCRx register.

Pointer increments

Peripheral and memory pointers can optionally be automatically post-incremented after

each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If

incremented mode is enabled, the address of the next transfer will be the address of the

previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer

address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During

transfer operations, these registers keep the initially programmed value. The current

transfer addresses (in the current internal peripheral/memory address register) are not

accessible by software. If the channel is configured in noncircular mode, no DMA request is

served after the last transfer (that is once the number of data items to be transferred has

reached zero). In order to reload a new number of data items to be transferred into the

DMA_CNDTRx register, the DMA channel must be disabled.

If a DMA channel is disabled, the DMA registers are not Reset. The DMA channel registers

(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during

the channel configuration phase.

In circular mode, after the last transfer, the DMA_CNDTRx register is automatically

reloaded with the initially programmed value. The current internal address registers are

reloaded with the base address values from the DMA_CPARx/DMA_CMARx registers.

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