AD8450ASTZ datasheet(30/42 Pages) AD

30 / 42 page

Data Sheet

AD8450

Rev. B | Page 29 of 41

APPLICATIONS INFORMATION

This section describes how to use the AD8450 in the context of

a battery formation and test system. This section includes a design

example of a small scale model of an actual system. An evaluation

board for the AD8450 is available and is described in the

Evaluation Board section.

FUNCTIONAL DESCRIPTION

The AD8450 is a precision analog front end and controller for

battery formation and test systems. These systems use precision

controllers and power stages to put batteries through charge and

discharge cycles. Figure 59 shows the signal path of a simplified

switching battery formation and test system using the AD8450

controller and the ADP1972 PWM controller. For more

information about the ADP1972, see the ADP1972 data sheet.

The AD8450 is suitable for systems that form and test NiCad,

NiMH, and Li-Ion batteries and is designed to operate in

conjunction with both linear and switching power stages.

The AD8450 includes the following blocks (see Figure 49 and

the Theory of Operation section for more information).



Pin programmable gain instrumentation amplifier (PGIA)

that senses low-side or high-side battery current.



Pin programmable gain difference amplifier (PGDA) that

measures the terminal voltage of the battery.



Two loop filter error amplifiers that receive the battery target

current and voltage and establish the dynamics of the constant

current (CC) and constant voltage (CV) feedback loops.



Minimum output selector circuit that combines the outputs

of the loop filter error amplifiers to perform automatic CC

to CV switching.



Output clamp amplifier that drives the VCTRL pin. The

voltage range of this amplifier is bounded by the voltage

at the VCLP and VCLN pins such that it cannot overrange

the subsequent stage. The output clamp amplifier can drive

switching and linear power converters. Note that an increas-

ing voltage at the VCTRL pin must translate to a larger

output current in the power converter.



Overcurrent and overvoltage comparators whose outputs are

combined using a NOR gate to drive the FAULT pin. The

FAULT pin presents a logic low when either comparator is

tripped.



2.5 V reference that can be used as the reference voltage for

the overcurrent and overvoltage comparators. The output

node of the 2.5 V reference is the VREF pin.



Current sharing amplifier that detects the maximum battery

current among several charging channels and whose output

can be used to implement current balancing.



Logic input pin (MODE) that changes the configuration of

the controller from charge to discharge mode. A logic high

at the MODE pin configures charge mode; a logic low

configures discharge mode.

POWER SUPPLY CONNECTIONS

The AD8450 requires two analog power supplies (AVCC and

AVEE), one digital power supply (DVCC), one analog ground

(AGND), and one digital ground (DGND). AVCC and AVEE

power all the analog blocks, including the PGIA, PGDA, op amps,

and comparators. DVCC powers the MODE input logic circuit

and the FAULT output logic circuit. AGND provides a reference

and return path for the 2.5 V reference, and DGND provides a

reference and return path for the digital circuitry.

The rated absolute maximum value for AVCC − AVEE is 36 V,

and the minimum operating AVCC and AVEE voltages are +5 V

and −5 V, respectively. Due to the high PSRR of the AD8450

analog blocks, AVCC can be connected directly to the high current

power bus (the input voltage of the power converter) without

risking the injection of supply noise to the controller outputs.

A commonly used power supply combination is +25 V and

−5 V for AVCC and AVEE, and +5 V for DVCC. The +25 V rail

for AVCC provides enough headroom to the PGIA such that it

can be connected in a high-side current sensing configuration

with up to four batteries in series (4S). The −5 V rail for AVEE

allows the PGDA to sense accidental reverse battery conditions

(see the Reverse Battery Conditions section).

Connect decoupling capacitors to all the supply pins. A 1 μF

capacitor in parallel with a 0.1 μF capacitor is recommended.

POWER SUPPLY SEQUENCING

As detailed in the absolute maximum ratings table (see Table 2),

the voltage at any input pin other than ISVP, ISVN, BVPx, and

BVNx cannot exceed the positive analog supply (AVCC) by

more than 0.5 V and cannot be exceeded by the analog negative

supply (AVEE) by 0.5V.

Additionally, supply and ground pins (DVCC, DGND, and

AGND) cannot exceed the positive analog supply (AVCC) by

more than 0.5 V and cannot be exceeded by the analog negative

supply (AVEE) by 0.5V.

Therefore, power-on and power-off sequencing may be

required to comply with the absolute maximum ratings.

Failure to comply with the absolute maximum ratings can result

in functional failure or damage to the internal ESD diodes.

Damaged ESD diodes can cause parametric failures and cannot

provide full ESD protection, reducing reliability.

POWER-ON SEQUENCE

To power on the device, take the following steps:

Turn on AVCC

Turn on AVEE

Turn on DVCC

Turn on the input signals

The positive analog supply (AVCC) and the negative analog

supply (AVEE) may be turned on simultaneously.

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