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PSD813F2 データシート(PDF) 86 Page - STMicroelectronics |
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PSD813F2 データシート(HTML) 86 Page - STMicroelectronics |
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86 / 110 page  PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 86/110 Figure 44. Input Macrocell Timing (product term clock) Table 53. Input Macrocell Timing (5V devices) Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX. Table 54. Input Macrocell Timing (3V devices) Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. Symbol Parameter Conditions -70 -90 -15 PT Aloc Turbo Off Unit Min Max Min Max Min Max tIS Input Setup Time (Note 1) 00 0 ns tIH Input Hold Time (Note 1) 15 20 26 + 10 ns tINH NIB Input High Time (Note 1) 912 18 ns tINL NIB Input Low Time (Note 1) 912 18 ns tINO NIB Input to Combinatorial Delay (Note 1) 34 46 59 + 2 + 10 ns Symbol Parameter Conditions -12 -15 -20 PT Aloc Turbo Off Unit Min Max Min Max Min Max tIS Input Setup Time (Note 1) 00 0 ns tIH Input Hold Time (Note 1) 25 25 30 + 20 ns tINH NIB Input High Time (Note 1) 12 13 15 ns tINL NIB Input Low Time (Note 1) 12 13 15 ns tINO NIB Input to Combinatorial Delay (Note 1) 46 62 70 + 4 + 20 ns tINH tINL tINO tIH tIS PT CLOCK INPUT OUTPUT AI03101 |
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