PSD813F2 datasheet(32/110 Pages) STMICROELECTRONICS

部品番号	PSD813F2

部品情報	Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

PDF	110 Pages

Scroll/Zoom	100%

メーカー	STMICROELECTRONICS [STMicroelectronics]

ホームページ	http://www.st.com

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32 / 110 page

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

32/110

PAGE REGISTER

The 8-bit Page Register increases the addressing

capability of the MCU by a factor of up to 256. The

contents of the register can also be read by the

MCU. The outputs of the Page Register (PGR0-

PGR7) are inputs to the DPLD decoder and can be

included

the

Sector

Select

(FS0-FS7,

CSBOOT0-CSBOOT3), and SRAM Select (RS0)

equations.

If memory paging is not needed, or if not all 8 page

these bits may be used in the CPLD for general

logic. See Application Note AN1154.

Figure 12 shows the Page Register. The eight flip-

flops in the register are connected to the internal

data bus D0-D7. The MCU can write to or read

from the Page Register. The Page Register can be

accessed at address location CSIOP + E0h.

Figure 12. Page Register

RESET

D0 - D 7

R/W

PAGE

PGR0

PGR1

PGR2

PGR3

DPLD

AND

CPLD

INTERNAL

SELECTS

AND LOGIC

PLD

PGR4

PGR5

PGR6

PGR7

AI02871B

PSD813F2 データシート(PDF) 32 Page - STMicroelectronics

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