SN65MLVD047

SLLS606 − MARCH 2004

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8

Y

Z

0 V or VCC

1.62 k

Ω , ±1%

VY, or VZ

Figure 7. Driver Maximum Steady State Output Voltage

tc(n)

1/f0

0 V

0 V

Period Jitter

0 V

Peak to Peak Jitter

1/f0

PRBS INPUT

OUTPUT

VY −VZ

VY −VZ

CLOCK

INPUT

IDEAL

OUTPUT

ACTUAL

OUTPUT

VCC

VCC/2

tjit(per) =tc(n) −1/f0

tjit(pp)

0 V

VCC

VCC/2

0 V

VY −VZ

VY −VZ

Cycle to Cycle Jitter

0 V

VY − VZ

OUTPUT

tc(n)

tc(n+1)

tjit(cc) = | tc(n) − tc(n+1) |

NOTES:A. All input pulses are supplied by an Agilent 8304A Stimulus System.

B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software

C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50

±1% duty cycle clock input.

D. Peak-to-peak jitter is measured using a 200 Mbps 215−1 PRBS input.

Figure 8. Driver Jitter Measurement Waveforms

DEVICE INFORMATION

PIN ASSIGNMENTS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

EN

1A

2A

VCC

GND

3A

4A

EN

1Z

1Y

2Y

2Z

3Z

3Y

4Y

4Z

PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

EN

1A

2A

VCC

GND

3A

4A

EN

1Z

1Y

2Y

2Z

3Z

3Y

4Y

4Z

D PACKAGE

(TOP VIEW)