AM29PDL128G datasheet(36/69 Pages) SPANSION

36 / 69 page

July 29, 2002

Am29PDL128G

P R E L I M I NARY

until the system issues the four-cycle Exit SecSi Sec-

tor command sequence. The Exit SecSi Sector com-

m a nd s equenc e retu rns th e dev ic e t o norm a l

operation. The SecSi Sector is not accessible when

the device is executing an Embedded Program or em-

bedded Erase algorithm. Tables 15 and 17 show the

address and data requirements for both command se-

quences. See also “SecSi™ (Secured Silicon) Sector

Flash Memory Region” for further information.

Double Word/Word Program Command

Sequence

The system may program the device by double word

or word, depending on the state of the WORD# pin.

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Tables 14 and 16 show the

address and data requirements for the program com-

mand sequence.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. Refer to the Write Operation

Status section for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a

“0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram data to a bank faster than using the standard

program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. That bank

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Tables 14 and 16 show the requirements

for the command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the bank

address and the data 90h. The second cycle need

only contain the data 00h. The bank then returns to

the read mode.

The device offers accelerated program operations

through the ACC pin. When the system asserts V

HH on

the ACC pin, the device automatically enters the Un-

lock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command se-

quence. The device uses the higher voltage on the

ACC pin to accelerate the operation. Note that the

ACC pin must not be at V

HH any operation other than

accelerated programming, or device damage may re-

sult. In addition, the ACC pin must not be left floating

or unconnected; inconsistent behavior of the device

may result.

Figure 3 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 16 for timing diagrams.

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