MB96310 datasheet(76/82 Pages) CYPRESS

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Document Number: 002-04592 Rev. *A

Page 75 of 81

MB96310 Series

15.2 Frequency dependency of power supply currents in PLL Run mode

The following diagrams show the current consumption of samples with typical wafer process parameters in PLL Run mode at different

frequencies and Flash timing settings.

Measurement conditions:

•VCC = AVCC = 5.0V

• Ta = 25°C

•fCLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram

•fCLKS2 = fCLKS1

•fCLKP1 = fCLKB

•fCLKP2 = fCLKB/2

• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram

• Main clock = 4MHz external clock

• Flash memory timing settings:

•MTCRA=2128H/2208H (0 Flash wait states, fCLKS1 = 2*fCLKB)

•MTCRA=0239H/2129H (1 Flash wait state, fCLKS1 = fCLKB)

•MTCRA=4C09H/6B09H (1 Flash wait state, fCLKS1 = 2*fCLKB)

•MTCRA=233AH (2 Flash wait states, fCLKS1 = fCLKB)

• Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit):

• 0 Flash wait states: 0.5

• 1 Flash wait states: 0.33

• 2 Flash wait states: 0.25

MB96F313/F315 PLL Run mode currents

121620242832364044485256

CLKB/CLKP1 (MHz)

1 Flash wait state

(CLKS1=2*CLKB, 1.9 V)

1 Flash wait state

(CLKS1=2*CLKB, 1.8 V)

0 Flash wait states

(CLKS1=2*CLKB, 1.8 V)

1 Flash wait state

(CLKS1=CLKB, 1.8V)

2 Flash wait states

(CLKS1=CLKB, 1.8 V)

2 Flash wait states

(CLKS1=CLKB, 1.9 V)

: Specified in "DC characteristics"

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