DS3153N datasheet(36/60 Pages) DALLAS

部品番号	DS3153N

部品情報	Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

PDF	60 Pages

Scroll/Zoom	100%

メーカー	DALLAS [Dallas Semiconductor]

ホームページ	https://www.maximintegrated.com/en.html

Logo

36 / 60 page

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

36 of 60

12.4 JTAG Test Registers

IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An

optional test register, the identification register, has been included in the device design. It is used with the IDCODE

instruction and the Test-Logic-Reset state of the TAP controller.

Bypass Register. This single 1-bit shift register, used with the BYPASS, CLAMP, and HIGHZ instructions,

provides a short path between JTDI and JTDO.

Boundary Scan Register. This register contains a shift register path and a latched parallel output for control cells

and digital I/O cells. DS315x BSDL files are available at www.maxim-ic.com/TechSupport/telecom/bsdl.htm.

Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output. It is

selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.

DS3153N データシート(PDF) 36 Page - Dallas Semiconductor