STA003T datasheet(30/32 Pages) STMICROELECTRONICS

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5.5 DAC RELATED REGISTERS CONFIGURA-

TION

The different DAC registers must be configured

for 48kHz audio frequency: this is the reference

frequency. The STA003T will use these parame-

ters to derivate the register configurations for the

other audio frequencies (32, 24, 16, 12, 8 KHz)

according to the bistream informations.

The STA003T DAC and PLL register must be

configured according to the following steps:

1) OCLK_Freq determination from the DAC over-

sampling factor O_FAC.

As all STA003T registers must be configured

for 48KHz reference frequency, the OCLK

frquency is:

OCLK_Freq = O_FAC

⋅ 48KHz

ex: O_FAC = 384, OCLK_Freq = 18.432MHz

2) PCMDIVIDER (0 x 54) register configuration.

The PCMDIVIDER register is used to config-

ure the frequency ratio between OCLK_Freq

and SCKT_Freq:

SCKT_Freq

OCLK_Freq

(2 ⋅ (1 + PCMDIVIDER))

The SCKT signal is the bit clock for the DAC

serial output. The SCKT frequency depends

on the number of bits to be transmitted to the

DAC during one LRCKT (Left/Right clock)

clock period. These number of bit depends on

the DAC precision (16, 18, 20 or 24bits) and

on the mode that is used to transmit the data

the

DAC

(see

figure

8).

Once

the

PCMCONF register is set according to the

DAC requirements, the number of SCKT clock

periods per LRCKT clock period is 16x2 or

32x2.

a) LRCKT_period = 16x2 SCKT_periods

SCKT_Freq = LRCKT_Freq

⋅ 32 =

OCLK_Freq

(2 ⋅ (1+PCMDIVIDER))

As the reference audio frequency is 48 KHz,

the previous relation becomes:

48KHz

⋅ 32 = 48kHz ⋅ O_FAC (2 ⋅ (1+ PCMDI-

VIDER))

Consequently:

PCMDIVIDER = (O_FAC/64)-1

ex: O_FAC = 384, PCMCONF[1:0] = 00,

PCMDIVIDER = 5

b) LRCKT_period = 32x2 SCKT_periods

SCKT_Freq = LRCKT_Freq

⋅ 64 =

OCLK_Freq

(2 ⋅ (1+PCMDIVIDER))

Consequently:

PCMDIVIDER = (O_FAC/128)-1

3) Configuration of the PLL registers to set

OCLK_FREQ to the desired value computed

in step 1.

The PLL configuration in direct relation with

the XTI input clock frequency (14.72 MHz).

OCLK_freq

= 



+ MFSDF(X)







⋅

⋅ 



14.72MHz

+ PLLCTL_N







⋅ 



PLLCTL_M

+1 +

PLLFRAC

65536







* MFSDF(X) is the value of the MFSDF(X)(0x61)

* PLLCTL_N is the value of the PLLCTL_N

(0x07) register.

* PLLCTL_M is the value of the PLLCTL_N

(0x07) register.

* PLLFRAC (decimal) is the value of the

PLLFRAC_H and PLLFRAC_L registers as

PLLFRAC

256

⋅

PLLFRAC_H

PLLFRAC_L.

The following table gives the possible values for

these registers according to different OCLK_Freq

values. Other values can be supported on re-

quest to STMicroelectronics.

O_FAC

OCLK_Freq

at 48KHz

PLLCTL_N

PLLCTL_M

PLLFRAC

MFSDF

128

6.144MHz

23365

256

12.288MHz

23365

384

18.432MHz

34193

STA003T

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