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IMX7SCEC データシート(PDF) 36 Page - NXP Semiconductors |
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IMX7SCEC データシート(HTML) 36 Page - NXP Semiconductors |
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36 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 36 4.2.1.5 LDO_SVNS_1P8 1.8 V LDO from coin cell to generate 1.8 V power for SNVS and 32 K RTC. The LDO_SNVS_1P8 regulator implements a fixed linear-regulator function from VDD_SNVS_IN (see Table 9 for minimum and maximum input requirements). The typical output is 1.7 V. It is intended for use with the internal SNVS circuitry and 32 K RTC. For additional information, see the i.MX 7Solo Application Processor Reference Manual (IMX7SRM). 4.3 PLL electrical characteristics 4.4 On-chip oscillators 4.4.1 OSC24M Power for the oscillator is supplied from a clean source of VDDA_1P8. This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements an oscillator. The oscillator is powered from VDDA_1P8. Table 20. PLL Electrical Parameters PLL type Parameter Value AUDIO_PLL Clock output range 650 MHz–1.3 GHz Reference clock 24 MHz Lock time <11250 reference cycles VIDEO_PLL Clock output range 650 MHz–1.3 GHz Reference clock 24 MHz Lock time <383 reference cycles SYS_PLL Clock output range 480 MHz Reference clock 24 MHz Lock time <383 reference cycles ENET_PLL Clock output range 650 MHz–1.3 GHz, set to 1.0 GHz Reference clock 24 MHz Lock time <11250 reference cycles ARM_PLL Clock output range 800 MHz–1.2 GHz Reference clock 24 MHz Lock time <2250 reference cycles DRAM_PLL Clock output range 800 MHz–1066 MHz Reference clock 24 MHz Lock time >2250 reference cycles |
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