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IMX7SCEC データシート(PDF) 96 Page - NXP Semiconductors |
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IMX7SCEC データシート(HTML) 96 Page - NXP Semiconductors |
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96 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 96 4.10.8.4 Possible ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals Figure 66. Possible ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals 4.10.8.5 MIPI PHY switching characteristics Table 70. Electrical and Timing Information Symbol Parameters Test Conditions Min Typ Max Unit HS Line Drivers AC Specifications — Maximum serial data rate (forward direction) On DATAP/N outputs. 80 Ω <= RL <= 125 Ω 80 — 1500 Mbps FDDRCLK DDR CLK frequency On DATAP/N outputs. 40 — 750 MHz PDDRCLK DDR CLK period 80 Ω<= RL< = 125 Ω 1.33 — 25 ns tCDC DDR CLK duty cycle tCDC = tCPH / PDDRCLK —50 — % tCPH DDR CLK high time — — 1 — UI tCPL DDR CLK low time — — 1 — UI — DDR CLK / DATA Jitter — — 75 — ps pk–pk tSKEW[PN] Intra-Pair (Pulse) skew — — 0.075 — UI tSKEW[TX] Data to Clock Skew — 0.350 — 0.650 UI tr Differential output signal rise time 20% to 80%, RL = 50 Ω 150 — 0.3UI ps tf Differential output signal fall time 20% to 80%, RL = 50 Ω 150 — 0.3UI ps ΔVCMTX(HF) Common level variation above 450 MHz 80 Ω<= RL< = 125 Ω —— 15 mVrms ΔVCMTX(LF) Common level variation between 50 MHz and 450 MHz. 80 Ω<= RL< = 125 Ω —— 25 mVp VOD(0) VOD(1) VOD/2 VOD/2 VOD (SE H S Signals) Static VCMTX (SE HS Signals) Dynamic VCMTX (SE HS Signals) VDN VCM TX VDP VDN VCMTX VDP VDN VCM TX VDP VOD(0) Δ Δ Δ Δ Δ |
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