4, 8 Meg x 64 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM83.p65 – Rev. 2/99

©1999, Micron Technology, Inc.

5

4, 8 MEG x 64

DRAM SODIMMs

STANDBY

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced

standby level. Also, the chip is preconditioned for the

next cycle during the RAS# HIGH time.

SERIAL PRESENCE-DETECT OPERATION

This module family incorporates serial presence-

detect (SPD). The SPD function is implemented using

a 2,048-bit EEPROM. This nonvolatile storage device

contains 256 bytes. The first 128 bytes can be pro-

grammed by Micron to identify the module type and

various DRAM organizations and timing parameters.

The remaining 128 bytes of storage are available for use

by the customer. System READ/WRITE operations be-

tween the master (system logic) and the slave EEPROM

device (DIMM) occur via a standard IIC bus using the

DIMM’s SCL (clock) and SDA (data) signals.

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (Fig-

ures 1 and 2).

SPD START CONDITION

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has

been met.

SPD STOP CONDITION

All communications are terminated by a stop con-

dition, which is a LOW-to-HIGH transition of SDA

when SCL is HIGH. The stop condition is also used to

place the SPD device into standby power mode.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to

indicate successful data transfers. The transmitting

device, either master or slave, will release the bus after

transmitting eight bits. During the ninth clock cycle,

the receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (Figure 3).

The SPD device will always respond with an ac-

knowledge after recognition of a start condition and

its slave address. If both the device and a WRITE

Figure 3

Acknowledge Response From Receiver

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

9

8

Acknowledge

Figure 2

Definition of Start and Stop

SCL

SDA

START

BIT

STOP

BIT

Figure 1

Data Validity

SCL

SDA

DATA STABLE

DATA STABLE

DATA

CHANGE