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LPC47M192 データシート(PDF) 40 Page - SMSC Corporation

部品番号 LPC47M192
部品情報  LPC SUPER I/O WITH HARDWARE MONITORING BLOCK
PDF  228 Pages
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メーカー  SMSC [SMSC Corporation]
ホームページ  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M192 データシート(HTML) 40 Page - SMSC Corporation

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SMSC DS – LPC47M192
Page 40
Rev. 03/30/05
DATASHEET
BITS 1 – 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual
data rates. The data rate select bits are
unaffected by
a software reset, and are set to 250 Kbps after a
hardware reset.
BITS 3 – 6 UNDEFINED
Always read as a logic “1”
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
Model 30 Mode
7
6
5
4
3
2
1
0
DSK CHG
0
0
0
DMAEN NOPREC DRATE
SEL1
DRATE
SEL0
RESET
COND.
N/A
0
0
0
0
0
1
0
BITS 0 – 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual
data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware
reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 – 6 UNDEFINED
Always read as a logic “0”
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
7
6
5
4
3
2
1
0
0
0
0
0
0
0
DRATE
SEL1
DRATE
SEL0
RESET
COND.
N/A
N/A
N/A
N/A
N/A
N/A
1
0
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values.
BIT 2 – 7 RESERVED
Should be set to a logical “0”



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