AM652X datasheet(175/299 Pages) TI1

175 / 299 page

175

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(7) For div_by_1_mode:

–

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX_133:

–

gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz

For TIMEPARAGRANULARITY_X1:

–

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME,

RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

Table 5-51. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode

NO.

PARAMETER

DESCRIPTION

MODE(15)

MIN

MAX

UNIT

tR(d)

Rise time, output data GPMC_AD[15:0]

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

tF(d)

Fall time, output data GPMC_AD[15:0]

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

FA0

tw(be[x]nV)

Pulse duration, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid time

Read

N (12)

Write

N (12)

FA1

tw(csnV)

Pulse duration, output chip select

GPMC_CSn[x](13) low

Read

A (1)

Write

A (1)

FA3

td(csnV-advnIV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

Read

-2+B (2)

2+B (2)

Write

-2+B (2)

2+B (2)

FA4

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output enable GPMC_OEn_REn invalid

(Single read)

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+C (3)

2+C (3)

FA9

td(aV-csnV)

Delay time, output address GPMC_A[27:1] valid to

output chip select GPMC_CSn[x](13) valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+J (9)

2+J (9)

FA10

td(be[x]nV-csnV)

Delay time, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid to output

chip select GPMC_CSn[x](13) valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+J (9)

2+J (9)

FA12

td(csnV-advnV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+K (10)

2+K (10)

FA13

td(csnV-oenV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+L (11)

2+L (11)

FA16

tw(aIV)

Pulse duration output address GPMC_A[26:1]

invalid between 2 successive read and write

accesses

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

G (7)

FA18

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output enable GPMC_OEn_REn invalid

(Burst read)

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+I (8)

2+I (8)

FA20

tw(aV)

Pulse duration, output address GPMC_A[27:1]

valid - 2nd, 3rd, and 4th accesses

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

D (4)

FA25

td(csnV-wenV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output write enable GPMC_WEn valid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+E (5)

2+E (5)

FA27

td(csnV-wenIV)

Delay time, output chip select GPMC_CSn[x](13)

valid to output write enable GPMC_WEn invalid

div_by_1_mode;

GPMC_FCLK_MUX_133;

TIMEPARAGRANULARITY_X1

-2+F (6)

2+F (6)

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