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AM652X データシート(PDF) 99 Page - Texas Instruments |
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AM652X データシート(HTML) 99 Page - Texas Instruments |
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99 / 299 page  99 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Terminal Configuration and Functions Copyright © 2017–2018, Texas Instruments Incorporated (1) These signals must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level. 4.3.26.2 Clock 4.3.26.2.1 MAIN Domain Table 4-67. Clock1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] OSC1_XI High frequency oscillator input I C22 OSC1_XO High frequency oscillator output O E22 4.3.26.2.2 WKUP Domain Table 4-68. Clock0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_LFOSC0_XI Low frequency (32.768 KHz) oscillator input I AE4 WKUP_LFOSC0_XO Low frequency (32.768 KHz) oscillator output O AC4 WKUP_OSC0_XI High frequency oscillator input I AD5 WKUP_OSC0_XO High frequency oscillator output O AE6 4.3.26.3 System 4.3.26.3.1 MAIN Domain Table 4-69. System0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EXT_REFCLK1 External clock input to Main Domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) I A22 NMIn External Interrupt I F18 OBSCLK0 Observation clock output for test and debug purposes only O C23 PORz Main Domain cold reset I E19 PORz_OUT Main Domain POR status output O C19 REFCLK0N SERDES Differential Clock Output (negative) O AF9 REFCLK0P SERDES Differential Clock Output (positive) O AF10 REFCLK1N SERDES Differential Clock Output (negative) O AE8 REFCLK1P SERDES Differential Clock Output (positive) O AE9 RESETSTATz Main Domain warm reset status output O D19 RESETz Main Domain warm reset I F17 SOC_SAFETY_ERRORn Error signal output from Main Domain ESM IO E20 SYNC0_OUT CPTS Time Stamp Generator Bit 0 O D21 SYNC1_OUT CPTS Time Stamp Generator Bit 1 O A22 SYNC2_OUT CPTS Time Stamp Generator Bit 2 O AE18 SYNC3_OUT CPTS Time Stamp Generator Bit 3 O AH17 SYSCLKOUT0 SYSCLK0 output from Main PLL controller (divided by 6) for test and debug purposes only O B22 |
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