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AM652X データシート(PDF) 224 Page - Texas Instruments |
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AM652X データシート(HTML) 224 Page - Texas Instruments |
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224 / 299 page  EDIO_DATA_OUT SPRSP08_TIMING_PRU_EDIO_DATA_OUT IEPIO4 EDC_SYNCx_OUT PRIEP4 PRIEP2 PRIEP3 EDIO_DATA_IN[7:0] SPRSP08_TIMING_PRU_IEP_01 PRIEP1 224 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Table 5-102. PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRIEP2 tw(EDC_SYNCx_OUTH) Pulse Duration, EDC_SYNCx_OUT High -2+20*P (1) ns PRIEP3 tsu(EDIO_DATA_IN- EDC_SYNCx_OUT) Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT active edge 20 ns PRIEP4 th(EDC_SYNCx_OUT- EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT active edge 20 ns (1) P = PRU-ICSS IEP clock source period. Figure 5-112. PRU_ICSSG PRU IEP SYNCx Timing Table 5-103. PRU_ICSSG IEP Timing Requirements - Digital IOs NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT IEPIO1 tw(EDIO_OUTVALIDL) Pulse Duration, EDIO_OUTVALID Low -2+14*P (1) ns IEPIO2 tw(EDIO_OUTVALIDH) Pulse Duration, EDIO_OUTVALID High -2+32*P (1) ns IEPIO3 td(EDIO_OUTVALID- EDIO_DATA_OUT) Delay time, EDIO_OUTVALID to EDIO_DATA_OUT 0 0+18*P (1) ns IEPIO4 tsk(EDIO_DATA_OUT) EDIO_DATA_OUT skew 5 ns (1) P = PRU-ICSS IEP clock source period. Figure 5-113. PRU_ICSSG PRU IEP Digital IOs Timing Table 5-104. PRU_ICSSG IEP Timing Requirements - LATCHx_IN NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRLA1 tw(EDC_LATCHx_INL) Pulse Duration, EDC_LATCHx_IN Low 2+3*P (1) ns PRLA2 tw(EDC_LATCHx_INH) Pulse Duration, EDC_LATCHx_IN High 2+3*P (1) ns |
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