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AD9858 データシート(PDF) 5 Page - Analog Devices

部品番号 AD9858
部品情報  1 GSPS Direct Digital Synthesizer
PDF  32 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9858 データシート(HTML) 5 Page - Analog Devices

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AD9858
Rev. A | Page 5 of 32
Parameter
Temp
Test
Level
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Full
IV
10
MHz
Minimum Clock Pulse Width Low (tPWL)
Full
IV
5.5
ns
Minimum Clock Pulse Width High (tPWH)
Full
IV
15
ns
Maximum Clock Rise/Fall Time
Full
IV
1
ms
Minimum Data Setup Time (tDS)
Full
IV
7
ns
Mimimum Data Hold Time (tDH)
Full
IV
0
ns
Maximum Data Valid Time (tDV)
Full
IV
20
ns
Parallel Control Bus
WR Minimum Low Time
Full
IV
3
ns
WR Minimum High Time
Full
IV
6
ns
WR Minimum Period
Full
IV
9
ns
Address to WR Setup (TASU)
Full
IV
3
ns
Address to WR Setup (TAHU)
Full
IV
0
ns
Data to WR Setup (TDSU)
Full
IV
3.5
ns
Data to WR Hold (TDHU)
Full
IV
0
ns
Miscellaneous Timing Specifications
REFCLK to SYNCLK
Full
V
2.5
ns
FUD to SYNCLK Setup Time
Full
IV
4
ns
FUD to SYNCLK Hold Time
Full
IV
0
ns
REFCLK to SYNCLK Delay
Full
IV
2.5
3
ns
FUD Rising Edge to Frequency Change
Single Tone Mode
25°C
IV
83
sysclk
cycles
Linear Sweep Mode
25°C
IV
99
sysclk
cycles
FUD Rising Edge to Phase Offset Change
25°C
IV
83
sysclk
cycles
1 The reference clock input is configured to accept a differential or single-ended sine wave input or a 3 V CMOS-level pulse input.
2 REFCLK input is internally dc biased. AC coupling should be used.
3 Reference clock frequency is selected to ensure second harmonic is out of the bandwidth of interest.
4 PD inputs sent @ 400 MHz, with divide-by-4 enabled.
5 The charge pump current is programmable in eight discrete steps, minimum value assumes current sharing.
6 For 0.75 V < VCP < CPVDD – 0.75 V.
7 These differential inputs are internally dc biased. AC coupling should be used.
8 The charge pump supply voltage can range from 4.75 V to 5.25 V.
9 Output interface is differential open collector.
10 For 1 dB output compression; input power measured at 50 Ω.



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