HT46R46 datasheet(8/42 Pages) HOLTEK

8 / 42 page

HT46R46/HT46C46/HT46R47/HT46C47

Rev. 1.00

December 28, 2004

Errors can occur. In other words, using the table read

instruction in the main routine and the ISR simulta-

neously should be avoided. However, if the table read

instruction has to be applied in both the main routine

and the ISR, the interrupt is supposed to be disabled

prior to the table read instruction. It will not be enabled

until the TBLH has been backed up. All table related

instructions require two cycles to complete the opera-

tion. These areas may function as normal program

memory depending upon the requirements.

Stack Register

- STACK

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 4 levels for the HT46R46/

HT46C46 or 6 levels for the HT46R47/HT46C47 and

are neither part of the data nor part of the program

space, and is neither readable nor writeable. The acti-

vated level is indexed by the stack pointer (SP) and is

neither readable nor writeable. At a subroutine call or in-

terrupt acknowledgment, the contents of the program

counter are pushed onto the stack. At the end of a sub-

routine or an interrupt routine, signaled by a return in-

struction (RET or RETI), the program counter is restored

to its previous value from the stack. After a chip reset,

the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a

²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 4

(HT46R47/HT46C46) or 6 (HT46R47/HT46C47) return

addresses are stored).

Data Memory

- RAM

The data memory is designed with 84

´8 bits

(HT46R46/HT46C46) or 85

´8 bits (HT46R47/HT46C47).

The data memory is divided into two functional groups:

special function registers and general purpose data

memory (64

´8). Most are read/write, but some are

read only.

The special function registers include the indirect ad-

dressing register (00H), timer/event counter

(TMR;0DH), timer/event counter control register

(TMRC;0EH), program counter lower-order byte regis-

ter (PCL;06H), memory pointer register (MP;01H), ac-

cumulator (ACC;05H), table pointer (TBLP;07H), table

higher-order byte register (TBLH;08H), status register

(STATUS;0AH), interrupt control register (INTC;0BH),

PWM data register (PWM;1AH), the A/D result register

(ADR;21H) for the HT46R46/HT46C46, the A/D result

lower-order byte register (ADRL;20H) for the

HT46R47/HT46C47, the A/D result higher-order byte

A/D control register (ADCR;22H), the A/D clock setting

PD;18H) and I/O control registers (PAC;13H,

PBC;15H, PDC;19H). The remaining space before the

40H is reserved for future expanded usage and reading

these locations will get

²00H². The general purpose

data memory, addressed from 40H to 7FH, is used for

data and control information under instruction com-

mands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by

²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer register (MP;01H).

S p e c i a l P u r p o s e

D A T A M E M O R Y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

I n d i r e c t A d d r e s s i n g R e g i s t e r

M P

A C C

P C L

T B L P

T B L H

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P D

P D C

P W M

A D R

A D C R

A C S R

: U n u s e d

R e a d a s " 0 0 "

3 F H

2 4 H

2 0 H

2 1 H

2 2 H

2 3 H

G e n e r a l P u r p o s e

D A T A M E M O R Y

( 6 4 B y t e s )

7 F H

4 0 H

RAM Mapping for the HT46R46/HT46C46

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