EPCQ32 datasheet(42/48 Pages) INTEL

42 / 48 page

1.9.2. Read Operation Timing

Figure 23.

Read Operation Timing Diagram

DATA0

nCS

DCLK

DATA

tnCLK2D

Add_Bit 0

BitN

BitN - 1

Bit 0

tCH

tCL

tODIS

Table 34.

Read Operation Parameters

Symbol

Parameter

Min

Max

Unit

fRCLK

Read clock frequency (from the FPGA or embedded

processor) for read bytes operations

—

MHz

Fast read clock frequency (from the FPGA or

embedded processor) for fast read bytes operation

—

100

MHz

tCH

DCLK

high time

—

tCL

DCLK

low time

—

tODIS

Output disable time after read

—

tnCLK2D

Clock falling edge to DATA

—

1.10. Programming and Configuration File Support

The Intel Quartus Prime software provides programming support for EPCQ devices.

When you select an EPCQ device, the Intel Quartus Prime software automatically

generates the Programmer Object File (.pof) to program the device. The software

allows you to select the appropriate EPCQ device density that most efficiently stores

the configuration data for the selected FPGA.

You can program the EPCQ device in-system by an external microprocessor using the

SRunner software driver. The SRunner software driver is developed for embedded

EPCQ device programming that you can customize to fit in different embedded

systems. The SRunner software driver reads .rpd files and writes to the EPCQ devices.

The programming time is comparable to the Intel Quartus Prime software

programming time. Because the FPGA reads the LSB of the .rpd data first during the

configuration process, the LSB of .rpd bytes must be shifted out first during the read

bytes operation and shifted in first during the write bytes operation.

Writing and reading the .rpd file to and from the EPCQ device is different from the

other data and address bytes.

During the ISP of an EPCQ device using the Intel FPGA Download CableIntel FPGA

Download Cable II, Intel FPGA Ethernet Cable, the cable pulls the nCONFIG signal low

to reset the FPGA and overrides the 10-kΩ pull-down resistor on the nCE pin of the

FPGA. The download cable then uses the interface pins depending on the selected AS

mode to program the EPCQ device. When programming is complete, the download

cable releases the interface pins of the EPCQ device and the nCE pin of the FPGA and

pulses the nCONFIG signal to start the configuration process.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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