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NUC505-YO2G データシート(PDF) 84 Page - Nuvoton Technology Corporation |
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NUC505-YO2G データシート(HTML) 84 Page - Nuvoton Technology Corporation |
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84 / 130 page  NUC505 July. 26, 2018 Page 84 of 130 Rev.1.08 Clock Controller 6.3 6.3.1 Overview The clock controller generates clocks for the whole chip. The clocks include AHB, APB and engine clocks for all of devices like USB device, USB host, UART and so on. There are two PLL clocks, PLL and APLL, derived from external HXT clock input. The PLL clock allows the processor to operate at a high internal clock frequency. Also, the APLL is used to generate more accuracy frequency for audio CODEC. They also implement the power control function, include the individually clock on or off control register, clock source selector and divider. These functions minimize the extra power consumption and the chip runs on the just right condition. In Power- down mode, the controller turns off the crystal oscillator to minimize the chip power consumption. |
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