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¡ Semiconductor

MSM80C85AHRS/GS/JS

Name

Address Branched To (1)

When Interrupt Occurs

Type Trigger

RST 7.5

3CH

34H

Rising edge (latched).

High level unitl sampled.

RST 6.5

RST 5.5

2CH

(2)

High level until sampled.

High level until sampled.

INTR

TRAP

Priority

2

3

4

5

1

24H

Rising edge and high level unit sampled.

Table 1 Interrupt Priority, Restart Address, and Sensitivity

Notes: (1) The processor pushes the PC on the stack before branching to the indicated

address.

(2) The address branched to depends on the instruction provided to the cpu

when the interrupt is acknowledged.

RESET IN

(Input)

Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops and release

power down mode. The data and address buses and the control lines are 3-stated during RESET and

because of the asynchronous nature of RESET IN, the processor's internal registers and flags may be

altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing

connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as

long as RESET IN is applied.

Symbol

Function

RESET OUT

(Output)

Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to

the processor clock and lasts an integral number of clock periods.

(Input)

clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal

operating frequency.

SID

(Input)

Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction

is executed.

SOD

(Output)

Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

+ 5 Volt supply

GND

Ground Reference.

CLK

(Output)