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MPC885ZP66 データシート(PDF) 41 Page - Freescale Semiconductor, Inc |
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MPC885ZP66 データシート(HTML) 41 Page - Freescale Semiconductor, Inc |
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41 / 92 page  MPC885/MPC880 Hardware Specifications, Rev. 3 41 Freescale Semiconductor Bus Signal Timing Table 13 shows the debug port timing for the MPC885/880. Figure 32 provides the input timing for the debug port clock. Figure 32. Debug Port Clock Input Timing Figure 33 provides the timing for the debug port. Figure 33. Debug Port Timings Table 13. Debug Port Timing Num Characteristic All Frequencies Unit Min Max D61 DSCK cycle time 3 × TCLOCKO UT - D62 DSCK clock pulse width 1.25 × TCLO CKOUT - D63 DSCK rise and fall times 0.00 3.00 ns D64 DSDI input data setup time 8.00 ns D65 DSDI data hold time 5.00 ns D66 DSCK low to DSDO data valid 0.00 15.00 ns D67 DSCK low to DSDO invalid 0.00 2.00 ns DSCK D61 D61 D63 D62 D62 D63 DSCK DSDI DSDO D64 D65 D66 D67 |
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