MPC885ZP66 datasheet(63/92 Pages) FREESCALE

63 / 92 page

MPC885/MPC880 Hardware Specifications, Rev. 3

Freescale Semiconductor

CPM Electrical Characteristics

Figure 63. Ethernet Transmit Timing Diagram

12.9 SMC Transparent AC Electrical Specifications

Table 25 provides the SMC transparent timings as shown in Figure 64.

Table 25. SMC Transparent Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

150

SMCLK clock period 1

1 SyncCLK must be at least twice as fast as SMCLK.

100

—

151

SMCLK width low

—

151A

SMCLK width high

—

152

SMCLK rise/fall time

—

153

SMTXD active delay (from SMCLK falling edge)

154

SMRXD/SMSYNC setup time

—

155

RXD1/SMSYNC hold time

—

TCLK1

128

TxD1

(Output)

128

TENA(RTS1)

(Input)

NOTES:

Transmit clock invert (TCI) bit in GSMR is set.

If RENA is negated before TENA or RENA is not asserted at all during transmit, then the

CSL bit is set in the buffer descriptor at the end of the frame transmission.

RENA(CD1)

(Input)

133

134

132

131

121

129

(NOTE 2)

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