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MPC885ZP133 データシート(PDF) 40 Page - Freescale Semiconductor, Inc |
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MPC885ZP133 データシート(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 92 page  MPC885/MPC880 Hardware Specifications, Rev. 3 40 Freescale Semiconductor Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC885/880. Figure 30 provides the PCMCIA output port timing for the MPC885/880. Figure 30. PCMCIA Output Port Timing Figure 31 provides the PCMCIA input port timing for the MPC885/880. Figure 31. PCMCIA Input Port Timing Table 12. PCMCIA Port Timing Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit Min Max Min Max Min Max Min Max P57 CLKOUT to OPx valid (MAX = 0.00 × B1 + 19.00) — 19.00 — 19.00 — 19.00 — 19.00 ns P58 HRESET negated to OPx drive 1 (MIN = 0.75 × B1 + 3.00) 1 OP2 and OP3 only. 25.70 — 21.70 — 14.40 — 12.40 — ns P59 IP_Xx valid to CLKOUT rising edge (MIN = 0.00 × B1 + 5.00) 5.00 — 5.00 — 5.00 — 5.00 — ns P60 CLKOUT rising edge to IP_Xx invalid (MIN = 0.00 × B1 + 1.00) 1.00 — 1.00 — 1.00 — 1.00 — ns CLKOUT HRESET Output Signals OP2, OP3 P57 P58 CLKOUT Input Signals P59 P60 |
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