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MPC885ZP133 データシート(PDF) 62 Page - Freescale Semiconductor, Inc

部品番号 MPC885ZP133
部品情報  Hardware Specifications
PDF  92 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC885ZP133 データシート(HTML) 62 Page - Freescale Semiconductor, Inc

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MPC885/MPC880 Hardware Specifications, Rev. 3
62
Freescale Semiconductor
CPM Electrical Characteristics
Figure 61. Ethernet Collision Timing Diagram
Figure 62. Ethernet Receive Timing Diagram
134
TENA inactive delay (from TCLK1 rising edge)
10
50
ns
138
CLKO1 low to SDACK asserted 2
—20
ns
139
CLKO1 low to SDACK negated 2
—20
ns
1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1.
2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 24. Ethernet Timing (continued)
Num
Characteristic
All Frequencies
Unit
Min
Max
CLSN(CTS1)
120
(Input)
RCLK1
121
RxD1
(Input)
121
RENA(CD1)
(Input)
125
124
123
127
126
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