GPLB30A

© Generalplus Technology Inc.

Proprietary & Confidential

13

JAN. 07, 2008

Version: 1.4

8. APPLICATION CIRCUITS

8.1. 1040 Dots LCD Driver, 65 Segments × 16 Commons, 1/5 Bias with External Serial SRAM, Regulator Disabled- (1)

GPLB30A

LCD Panel (16x65)

SEG0

SEG1

SEG14

SEG2

SEG15

PA1

PA2

PA3

PA4

PA5

.....

.....

.....

.....

.....

V1

V2

V3

V4

CUP2

CUP1

CUP3

CUP4

VDD

VDD

VSS

SCK

SDA

CSB

PC1/SDA

PC0/SCK

PA7

VDD

GPRS512C

VLCD

.....

.....

PA6

VROUT

*1

VDD

RESET

PVDD

PVSS

AUDB

X32I

X32O

AUDA

VDD

30pF

C

*3

C

C

C

C

C

C

4.7

μF0.1μF

20pF

*2

20pF

*2

0.1

μF

Note*1: Pin VROUT should be connected to VDD if internal Regulator is disabled.

Note*2: These capacitor values are for design guidance only.

Different capacitor values may be required for different crystal/resonator used.

Note*3: The value of the capacitance(C) would range from 0.1

μF to 4.7μF to stable the output voltage.