GPR25L25605F datasheet(5/61 Pages) GENERALPLUS

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GPR25L25605F

Proprietary & Confidential

Jan 21, 2013

Version: 1.0

for erase command is executed on sector (4K-byte), block

(32K-byte), or block (64K-byte), or whole chip basis.

To provide user with ease of interface, a status register is included

to indicate the status of the chip. The status read command can

be issued to detect completion status of a program or erase

operation via WIP bit.

Advanced security features enhance the protection and security

functions, please see security features section for more details.

When the device is not in operation and CS# is high, it is put in

standby mode.

The GPR25L25605F utilizes proprietary memory cell, which

reliably stores memory contents even after 100,000 program and

erase cycles.

Table 1. Read Performance Comparison

Numbers

Dummy Cycles

Fast Read (MHz)

Dual Output Fast

Read (MHz)

Quad Output Fast

Read (MHz)

Dual IO Fast Read

(MHz)

Quad

Fast

Read (MHz)

84*

104

84*

104*

104

133

Note:

*means default status

3. PIN CONFIGURATIONS

3.1. 16-PIN SOP (300mil)

4. PIN DESCRIPTION

Symbol

Description

CS#

Chip Select

SI/SIO0

Serial Data Input (for 1 x I/O)/ Serial Data

Input & Output (for 2xI/O or 4xI/ O read mode)

SO/SIO1

Serial Data Output (for 1 x I/O)/ Serial Data

Input & Output (for 2xI/O or 4xI/ O read mode)

SCLK

Clock Input

WP#/SIO2

Write protection: connect to GND or Serial

Data Input & Output (for 4xI/O read mode)

NC/SIO3

No Connection or Serial Data Input &

Output (for 4xI/O read mode)

RESET#*

Hardware Reset Pin Active low

VCC

+ 3V Power Supply

GND

Ground

No Connection

Note:

RESET# pin has internal pull up.

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