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STUSB4710AQ1TR データシート(PDF) 17 Page - STMicroelectronics |
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STUSB4710AQ1TR データシート(HTML) 17 Page - STMicroelectronics |
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17 / 34 page ![]() STUSB4710 I²C interface DocID030499 Rev 4 17/34 Figure 5: Read operation Figure 6: Write operation 5.2 Timing specifications The device uses a standard slave I²C channel at speed up to 400 kHz. Table 9: I2C timing parameters - VDD = 5 V Symbol Parameter Min. Typ. Max. Unit Fscl SCL clock frequency 0 - 400 kHz thd,sta Hold time (repeated) START condition 0.6 - - µs tlow LOW period of the SCL clock 1.3 - - µs thigh HIGH period of the SCL clock 0.6 - - µs tsu,dat Setup time for repeated START condition 0.6 - - µs thd,dat Data hold time 0.04 - 0.9 µs tsu,dat Data setup time 100 - - µs tr Rise time of both SDA and SCL signals 20 + 0.1 Cb - 300 ns tf Fall time of both SDA and SCL signals 20 + 0.1 Cb - 300 ns tsu,sto Setup time for STOP condition 0.6 - - µs tbuf Bus free time between a STOP and START condition 1.3 - - µs Cb Capacitive load for each bus line - - 400 pF |
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