7

SCD5031 Rev B

Pre

lim

in

ar

y

DETAILED COMPONENT OPERATION AND PERFORMANCE

POWER SUPPLIES

Three I/O pins are used to supply power to the chip:

1) Two DRVP (referenced to DRVN) for the output stage.

conditions.

For protection against inadvertent over/undervoltages, the chip’s input pins are diode clamped to the supply rails through

current limiting resistors.

Undervoltage Lockout

The chip includes an internal undervoltage lockout circuit with built in hysteresis and a logic level power good indicator.

The positive and negative going thresholds are nominally 4.1V and 3.5V, respectively. If Vcc is below this range, the

oscillator, error amplifier, main comparators, and output drive circuits are all disabled. The power OK indicator is active

high (logic ''1'') when a valid supply voltage is applied.

Shutdown Logic

The chip has two logic level inputs for implementing shutdown functions. Asserting a logic ''1'' on the SLEEP pin disables

all chip functions and puts the chip into a very low power consumption mode. Asserting a logic ''0'' on the EN pin shuts

down all functions except the reference, bias generators, and auxiliary amplifier.

INPUTS

OUTPUTS

Sleep

EN

ENAUX

OUTA&B

AOUT

COMP

PWROK

Vref

0

0

0

0

0

0

Active

00

1

0

Active

0

Active

0

1

0

Active

0

Active

Active

0

1

1

Active

Active

Active

Active

1

X

X

0

0

000

1

X

X

0

0

000

1

X

X

0

0

000

1

X

X

0

0

000

Truth Table

3.5V

Von

Voff

4.1V

Vcc

POWER OK

ON/OFF COMMAND

TO REST OF IC

24

1.6mA

1

FIGURE 2 –Undervoltage Lockout