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AM652X データシート(PDF) 196 Page - Texas Instruments |
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AM652X データシート(HTML) 196 Page - Texas Instruments |
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196 / 277 page  196 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated Table 5-62 and Figure 5-63 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-62. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT I16 tc(SCL) Cycle time, SCL Standard 10000 ns Fast 2500 ns I17 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) Standard 4700 ns Fast 600 ns I18 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) Standard 4000 ns Fast 900 ns I19 tw(SCLL) Pulse duration, SCL low Standard 4700 ns Fast 1300 ns I20 tw(SCLH) Pulse duration, SCL high Standard 4000 ns Fast 600 ns I21 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high Standard 250 ns Fast 100 (2) ns I22 th(SCLL-SDAV) Hold time, SDA valid after SCL low Standard 0 (3) 3450 (4) ns Fast 0 (3) 900 (4) ns I23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions Standard 4700 ns Fast 1300 ns I24 tr(SDA) Rise time, SDA Standard 1000 ns Fast 20+.1Cb (5) (7) 300 (3) (7) ns I25 tr(SCL) Rise time, SCL Standard 1000 ns Fast 20+.1Cb (5) (7) 300 (3) (7) ns I26 tf(SDA) Fall time, SDA Standard 300 ns Fast 20+.1Cb (5) (7) 300 (3) (7) ns I27 tf(SCL) Fall time, SCL Standard 300 ns Fast 20+.1Cb (5) (7) 300 (3) (7) ns I28 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) Standard 4000 ns Fast 600 ns I29 tskew Skew Standard 3 ns Fast 20 ns I30 Cb Capacitive load for each bus line Standard 400 pF Fast 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the devive is powered down. (2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. (6) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the device TRM for details. (7) These timings apply only to MCU_I2C0 and WKUP_I2C0. MAIN_I2C[0:3] use standard LVCMOS buffers to emulate open-drain buffers and their rise/fall times should be referenced in the device IBIS model. |
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