AM652X datasheet(199/277 Pages) TI1

199 / 277 page

ASP8

ASP7

ASP4

ASP3

ASP2

ASP1

A30 A31

B30 B31 C0

C1 C2 C3

C31

MCASP[x]_ACLKR/X (Falling Edge Polarity)

MCASP[x]_AHCLKR/X (Rising Edge Polarity)

MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)

MCASP[x]_AXR[x] (Data In/Receive)

ASP6

ASP5

MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)

(A)

MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)

(B)

199

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP

receiver is configured for falling edge (to shift data in).

For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP

receiver is configured for rising edge (to shift data in).

Figure 5-64. MCASP Input Timing

(1) x in MCASP[x]_* is 0, 1 or 2

AM652X データシート(PDF) 199 Page - Texas Instruments

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