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AM652X データシート(PDF) 243 Page - Texas Instruments

部品番号 AM652X
部品情報  Processors Silicon Revision 1.0
PDF  277 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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AM652X データシート(HTML) 243 Page - Texas Instruments

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AM6548, AM6528, AM6546
AM6526, AM6527
www.ti.com
SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019
Submit Documentation Feedback
Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527
Detailed Description
Copyright © 2017–2019, Texas Instruments Incorporated
This module provides accurate timing of events. When not being used for event capture, its resources can
be used to generate a single channel of asymmetrical PWM waveforms (configurable as either one
capture input, or as one auxiliary PWM output).
6.3.1.5
PRU_ICSSG PWM Module
Each of the PRU_ICSSG modules integrates one Pulse Width Modulation module (PWM). The PWM
module uses the PRU_ICSSG IEP0 and IEP1 compare events to produce the PWM outputs.
6.3.1.6
PRU_ICSSG MII_G_RT Module
The Real-time Media Independent Interface (MII_G_RT) provides a programmable I/O interface for the
PRUs to access and control up to two MII ports. The MII_G_RT module can also be configured to push
and pull data independent of the PRU cores.
6.3.1.7
PRU_ICSSG MII MDIO Module
The PRU_ICSSG MII MDIO management I/F module implements the 802.3 serial management interface
to interrogate and control two Ethernet PHYs simultaneously using a shared two-wire bus.
6.3.1.8
PRU_ICSSG IEP
The Industrial Ethernet Peripheral (IEP) performs hardware work required for Industrial Ethernet functions.
The IEP module features an industrial ethernet timer with 16 compare events, industrial ethernet sync
generator and latch capture, industrial ethernet watchdog timer, and a digital I/O port (DIGIO).
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystem - Gigabit (PRU_ICSSG) section in the device TRM.
6.3.2
GPU
The Graphics Processing Unit (GPU) accelerates 2-dimensional (2D) and 3-dimensional (3D) graphics
and compute applications.
The GPU module is a scalable architecture which efficiently processes a number of differing multimedia
data types concurrently:
Pixel Data
Vertex Data
General Purpose Processing
For more information, see Graphics Accelerator (GPU) section in the device TRM.



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